A regular layout for parallel adders

Brent, Richard P.; Kung, H. T.

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A regular layout for parallel adders

Date

2015-01-01

Authors

Brent, Richard P.

Kung, H. T.

Abstract

With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show’ that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.