2.5 v 43-45 Gb/s CDR circuit and 55 Gb/s PRBS generator in SiGe using a low-voltage logic family

Abstract

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an XOR gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43-45 Gb/s CDR circuit with a 600 MHz locking range and a 55 Gb/s PRBS generator with a 2 7 -1 sequence length. The circuits were fabricated in a SiGe BiCMOS technology with f T = 120 GHz. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively. Show more